ADCs are a common component of many electronic devices. Conventional ADCs are based on time sampling of the analogue input signal, the converted digital signal being dependent on the value of the analogue signal at each time instant at which the analogue input signal is sampled. This results in a number of drawbacks of conventional ADCs. As analogue to digital conversion takes place at a number of discrete, spaced time instants, it is not possible to determine the analogue input signal value between two sampling time instants. For time-varying analogue input signals, unnecessary conversions to digital signals are performed when the analogue input signals are, temporarily, nearly constant. At each sampling time instant, the digital signal is produced from scratch by conversion of the value of the analogue input signal at the time instant, and the resultant digital signal cannot be predicted. The consequence of this is that it is necessary to carry out a sophisticated set of operations to convert the analogue input signal, each time this signal is sampled, regardless of what operations have been performed in conversions of the analogue input signal at previous time instants. This necessitates the use of complex ADC architecture, to perform complex analogue/digital operations. Such ADCs have undesirably high power consumption and large size. Optimisation of ADC operational characteristics (power consumption, size, resolution, speed, etc.) and also cost, is therefore of great importance.
One example where such ADC optimisation is particularly desirable is in portable devices, such as cellular phones, laptops and heart pacemakers, where it is important to conserve the power of the usually lifetime-limited power source, e.g. a battery. In cellular phone and laptop portable devices, there is a need to continuously monitor the voltage of the battery of the device, preferably both during an operational mode and a stand-by mode of the device. This is desired by many functions of the power management integrated circuit (PMIC) of the device. Monitoring of the battery voltage requires an ADC which is sufficiently fast to track rapid changes of the voltage, and which can avoid reaction to unwanted voltage spikes. Such an ADC function may be provided by running software conversions through the high resolution, general purpose ADC found on the PMIC of the device. However, this ADC uses conventional time-sampling of the battery voltage analogue signal, which requires use of a clock. Such use by the ADC, results in a not inconsequential power consumption by the ADC function. In addition, during the stand-by mode of the device, the only available clock is provided by a low frequency crystal oscillator. Such a low frequency clock cannot be used in the ADC function, so monitoring of the voltage of the battery is interrupted. Thus there is a need for an ADC which addresses these problems.
In pacemakers, the power source (battery) is not readily accessible for recharging or replacing. It is therefore of critical importance to limit, as much as possible, the power consumption of the battery. This is not entirely achievable by use of conventional ADCs and associated clocks.